In a NAND flash memory configured to enable data to be electrically rewritten, MOS transistors of a stack gate structure including a stack of a charge accumulation layer (floating gate) and a control gate are used as nonvolatile memory elements (flash memory cells). For example, data is written to a flash memory cell by injecting electrons into the floating gate. Data is read (read operation) by allowing a sense amplifier to sense a cell current that varies depending on whether or not electrons are injected into the floating gate.
In recent years, in connection with NAND flash memories, much attention has been paid to multilevel flash memories configured to enable a reduction in bit unit price or an increase in memory capacity per memory chip. In a multilevel flash memory, data of a plurality of bits with different thresholds is stored in one flash memory cell. For example, if 2-bit data is stored in each flash memory cell, the flash memory cell comprises four threshold zones (voltage distribution) corresponding to the data. In order to obtain more reliable devices, it is important to accurately control the threshold of the flash memory cell.
As a technique to accurately control the threshold of the flash memory cell, a method has been proposed which involves dividing a write voltage (Vpgm) into a plurality of write pulses and repeatedly writing data with the voltage of each of the write pulses stepped up at a given rate. The threshold of the flash memory cell, which varies in response to every application of a write pulse, is checked (verified). When the threshold reaches a prescribed verify level, the application of the write pulse is stopped to terminate the write. For example, if the step up voltage (AVpgm) of the write pulse is 0.2 V, the distribution width of each threshold can in principle be controlled to 0.2 V. A reduction in the rate of the step-up voltage enables the distribution width of the threshold to be reduced. However, in this case, more write pulses are required, disadvantageously resulting in a longer write time.
On the other hand, miniaturized NAND flash memories have contributed to reducing the distance between flash memory cells. Thus, a disadvantageous variation in the threshold of the flash memory cell has been prominent which results from the capacitive coupling between the adjacent floating gates. This may reduce the difference in threshold between the flash memories (read margin).
As a method for avoiding this problem, a quick pass write (hereinafter referred to as QPW) operation has been proposed (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-196988). In the proposed QPW operation, for example, first, a write voltage and a write control voltage are supplied to a memory cell to write data to the memory cell. Then, if the threshold of the memory cell reaches a first write state, the supply state of the write control voltage is changed to allow data to be repeatedly written to the memory cell. Then, if the threshold of the memory cell reaches a second write state, the supply state of the write control voltage is further changed to inhibit writes to the memory cell. That is, the QPW operation enables the threshold distribution width resulting from the write to be reduced with an increase in write time suppressed.
However, miniaturized NAND flash memories have disadvantageously contributed to increasing the amount of leakage current from bit lines. For example, in the QPW operation, the potential level of a bit line connected to a non-write flash memory cell is fixed to a voltage VDDSA before application of a write pulse. Then, the potential level of the bit line is brought into a floating state. A possible leakage current may reduce the potential level of the bit line during application of the write pulse. This increases the magnitude of the electric field (potential difference) between a channel region and the floating gate in the corresponding flash memory cell. That is, a decrease in the potential level of the bit line during application of the write pulse may vary the threshold of the flash memory cell. Thus, in the conventional QPW operation, an increase in the amount of leakage current may cause program disturbance (miswrites).